1. Field of the Invention
The present invention relates generally to photoresist layers employed in integrated circuit fabrication. More particularly, the present invention relates to methods for removing from semiconductor substrates photoresist layers which have become fluorinated in the process of integrated circuit fabrication.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
In the process of connecting and interconnecting electrical circuit elements with patterned conductor layers which are separated by dielectric layers within integrated circuits, it is common in the art of integrated circuit fabrication to form vias and other apertures through those dielectric layers such that conductive connections may be made between the patterned conductor layers and the electrical circuit elements which are separated by the dielectric layers. Although vias and other apertures within and/or through dielectric layers within integrated circuits may be formed through photolithographic methods followed by etch methods including but not limited to wet chemical etch methods and reactive ion etch (RIE) dry plasma etch methods, it has become quite common in the art that vias and other apertures formed within and/or through dielectric layers within integrated circuits will typically be formed through reactive ion etch (RIE) dry plasma etch methods. Since dielectric layers within integrated circuits are typically formed from silicon containing dielectric materials such as but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials, it is consequently also common in the art of integrated circuit fabrication that reactive ion etch (RIE) dry plasma etch methods which are employed in forming vias and other apertures within and/or through dielectric layers formed of those silicon containing dielectric materials will typically employ fluorine containing reactive ion etch (RIE) plasma etchants. Fluorine containing reactive ion etch (RE) plasma etchants are preferably employed since upon reaction with dielectric layers formed of silicon containing dielectric materials they form volatile species which are readily exhausted from reactive ion etch (RIE) plasma etch chambers.
While vias and other apertures within and/or through silicon containing dielectric layers may typically be effectively etched by means of fluorine containing reactive ion etch (RIE) plasma etch methods, fluorine containing reactive ion etch (RIE) plasma etch methods are not without problems in etching within integrated circuits dielectric layers formed of silicon containing materials. In particular, fluorine containing reactive ion etch (RIE) plasma etch methods are known in the art of integrated circuit fabrication to partially fluorinate patterned photoresist layers which are employed as etch masks through which vias and/or apertures within and/or through silicon containing dielectric layers within integrated circuits are patterned. The partially fluorinated patterned photoresist layers formed through fluorine containing reactive ion etch (RIE) plasma etch methods typically have a fluorinated surface layer of the partially fluorinated patterned photoresist layer and a non-fluorinated underlying remainder layer of the partially fluorinated patterned photoresist layer.
The fluorinated surface layers of partially fluorinated patterned photoresist layers are often difficult to effectively remove through either high power oxygen dry plasma photoresist stripping methods or wet chemical photoresist stripping methods as are known in the art. For example, when fluorinated surface layers of partially fluorinated patterned photoresist layers are removed through high power oxygen dry plasma photoresist stripping methods, damage often occurs to exposed layers adjoining the fluorinated surface layers. In contrast, under circumstances where a fluorinated surface layer of a partially fluorinated patterned photoresist layer is dislodged by dissolving in a wet chemical photoresist stripping solution a non-fluorinated underlying remainder layer of the partially fluorinated patterned photoresist layer, the fluorinated surface layer of the partially fluorinated patterned photoresist layer often redistributes upon the surface of the integrated circuit from which it was dislodged, thus obscuring the features of the integrated circuit from further processing. By obscuring features of the integrated circuit from further processing, it often becomes difficult to form fully functional or reliable integrated circuits Moreover, when a substantial concentration of portions of fluorinated surface layers of partially fluorinated patterned photoresist layers remains in a wet chemical photoresist stripping solution, the active lifetime of the wet chemical photoresist stripping solution is decreased. Finally, the lifetime of a recirculating filter employed in purifying the wet chemical photoresist stripping solution having contained therein the substantial concentration of fluorinated surface portions of partially fluorinated patterned photoresist layers is also decreased.
Beyond the foregoing problems generally encountered when removing fluorinated surface layers of partially fluorinated patterned photoresist layers formed incident to patterning through fluorine containing reactive ion etch (RIE) methods silicon containing dielectric layers within integrated circuits, additional problems are often encountered when the fluorinated surface layers of the partially fluorinated patterned photoresist layers are formed incident to patterning through fluorine containing reactive ion etch (RIE) methods silicon containing dielectric layers to form vias accessing metal contact layers within integrated circuits. Under such circumstances, there is typically formed, in addition to the fluorinated surface layer of the partially fluorinated patterned photoresist layer, a metal-polymer residue layer upon the sidewalls of both: (1) the via formed through the silicon containing dielectric layer; and (2) the partially fluorinated patterned photoresist layer employed in defining the via formed through the silicon containing dielectric layer. A schematic cross-sectional diagram illustrating such an integrated circuit structure is shown in FIG. 10.
Shown in FIG. 10 is a metal contact layer 40 having formed thereupon a pair of patterned silicon containing dielectric layers 42a and 42b. The pair of patterned silicon containing dielectric layers 42a and 42b is formed through patterning a blanket silicon containing dielectric layer through a fluorine containing reactive ion etch (RIE) plasma etch method while employing a patterned photoresist layer as an etch mask layer. Through exposure to the fluorine containing reactive ion etch (RIE) plasma etch method, there is formed from the patterned photoresist layer a pair of partially fluorinated patterned photoresist layers 45a and 45b comprising: (1) a pair of fluorinated surface layers 46a and 46b of the pair of partially fluorinated patterned photoresist layers 45a and 45b; and (2) a pair of non-fluorinated underlying remainder layers 44a and 44b of the pair of partially fluorinated patterned photoresist layers 45a and 45b. Finally, there is shown in FIG. 10 the presence of a pair metal-polymer residue layers 48a and 48b formed upon the sidewalls of: (1) the patterned silicon containing dielectric layers 42a and 42b; and (2) the partially fluorinated patterned photoresist layers 45a and 45b.
When it is attempted to remove the fluorinated surface layers 46a and 46b of the partially fluorinated patterned photoresist layers 45a and 45b through a high power oxygen plasma etch method as is conventional in the art of integrated circuit fabrication, the metal-polymer residue layers 48a and 48b are often sufficiently oxidized such that they are not readily subsequently removed through wet chemical stripping methods through which they would otherwise subsequently conventionally be removed. Alternatively, when it is attempted to remove the fluorinated surface layers 46a and 46b of the partially fluorinated patterned photoresist layers 45a and 45b through dissolution within a wet chemical stripping solution of the non-fluorinated underlaying remainder layers 44a and 44b of the partially fluorinated patterned photoresist layers 45a and 45b, there is often encountered an integrated circuit structure analogous to the integrated circuit structure whose schematic cross-sectional diagram is illustrated in FIG. 11.
Shown in FIG. 11 is the presence of a pair of partially dissolved non-fluorinated underlying remainder layers 44a' and 44b' within a pair of partially dissolved partially fluorinated patterned photoresist layers 45a' and 45b', where the pair of partially dissolved non-fluorinated underlying remainder layers 44a' and 44b' has the pair of fluorinated surface layers 46a and 46b remaining thereupon. Also shown in FIG. 11 is a dislodged and redistributed fluorinated surface layer 46c which has dislodged within the wet chemical photoresist stripping solution and redistributed upon the surface of the metal contact layer 40, thus occluding a portion of the surface of the metal contact layer 40 and assisting in forming a corroded metal contact layer 40'. Thus, it is in part towards the goal of avoiding the formation within integrated circuits of corroded metal contact layers, such as the corroded metal contact layer 40', that the present invention is in part directed.
In a more general sense, it is also an object of the present invention to provide a method for removing from a patterned silicon containing dielectric layer within an integrated circuit a partially fluorinated patterned photoresist layer in a fashion such that: (1) layers surrounding the partially fluorinated patterned photoresist layer are not damaged; (2) the partially fluorinated patterned photoresist layer does not leave a residue which impedes formation of a fully functional or reliable integrated circuit; or (3) a metal-polymer residue layer which typically forms upon the sidewall of a via formed through the patterned silicon containing dielectric layer to a metal contact layer while employing the partially fluorinated patterned photoresist layer as an etch mask is not sufficiently oxidized to make the metal-polymer residue layer difficult to remove from the integrated circuit.
Methods through which anti-reflection coating (ARC) halocarbon plasma polymers, such as fluorocarbon plasma polymers, may be formed upon and removed from integrated circuits have been disclosed in the art of integrated circuit fabrication. For, example, Bariya, in U.S. Pat. No. 5,443,941 discloses a method for removing from a semiconductor substrate a fluorocarbon plasma polymer through an oxygen plasma etching and ashing method.
More pertinent to the present invention, however, is a related co-assigned and partially co-invented application, serial number 08/660,302, filed Jun. 7, 1996, now U.S. Pat. No. 5,702,867 entitled "Soft Ashing Method for Removing Fluorinated Photoresist Layers From Semiconductor Substrates." While the method disclosed and claimed within the related co-assigned and partially co-invented application provides advantages with respect to removing fluorinated surface layers of partially fluorinated patterned photoresist layers within integrated circuits, the method as disclosed and claimed within the related co-assigned and partially co-invented application suffers from some deficiencies in optimally removing fluorinated surface layers of partially fluorinated patterned photoresist layers from upon patterned silicon containing dielectric layers having vias formed therethrough accessing metal contact layers, while limiting oxidation of metal-polymer residues formed upon the via sidewalls. It is thus towards providing a more optimal method for removing fluorinated surface layers of partially fluorinated patterned photoresist layers formed within integrated circuits within which there are also formed metal-polymer residue layers that the present invention is more specifically directed.
Thus, desirable in the art are additional methods through which partially fluorinated photoresist layers may be removed from integrated circuits. Similarly, particularly desirable are methods through which may be sequentially removed a fluorinated surface layer of a patterned partially fluorinated photoresist layer and a non-fluorinated underlying remainder layer of the patterned partially fluorinated photoresist layer from upon a patterned silicon containing dielectric layer having a via formed therethrough accessing a metal contact layer within an integrated circuit, without: (1) damaging integrated circuit layers adjoining the patterned partially fluorinated photoresist layer; (2) forming a residue which impedes the production of a fully functional and reliable integrated circuit; or (3) oxidizing a metal-polymer residue which typically forms upon the sidewall of the via formed through the silicon containing dielectric layer to the metal contact layer beneath the silicon containing dielectric layer.